ÿØÿà JFIF    ÿÛ „  ( %"1!%)+...383,7(-.+  -+++--++++---+-+-----+---------------+---+-++7-----ÿÀ  ß â" ÿÄ     ÿÄ H    !1AQaq"‘¡2B±ÁÑð#R“Ò Tbr‚²á3csƒ’ÂñDS¢³$CÿÄ   ÿÄ %  !1AQa"23‘ÿÚ   ? ôÿ ¨pŸªáÿ —åYõõ\?àÒü©ŠÄï¨pŸªáÿ —åYõõ\?àÓü©ŠÄá 0Ÿªáÿ Ÿå[úƒ ú®ði~TÁbqÐ8OÕpÿ ƒOò¤Oè`–RÂáœá™êi€ßÉ< FtŸI“öÌ8úDf´°å}“¾œ6  öFá°y¥jñÇh†ˆ¢ã/ÃÐ:ªcÈ "Y¡ðÑl>ÿ ”ÏËte:qž\oäŠe÷󲍷˜HT4&ÿ ÓÐü6ö®¿øþßèô Ÿ•7Ñi’•j|“ñì>b…þS?*Óôÿ ÓÐü*h¥£ír¶ü UãSç‚Ÿ[AÐaè[ûª•õ&õj?†Éö+EzP—WeÒírJFt ‘BŒ†Ï‡%#tE Øz ¥OÛ«!1›üä±Í™%ºÍãö]°î(–:@<‹ŒÊö×òÆt¦ãº+‡¦%ÌÁ²h´OƒJŒtMÜ>ÀÜÊw3Y´•牋4ǍýʏTì>œú=Íwhyë,¾Ôò×õ¿ßÊa»«þˆѪQ|%6ž™A õ%:øj<>É—ÿ Å_ˆCbõ¥š±ý¯Ýƒï…¶|RëócÍf溪“t.СøTÿ *Ä¿-{†çàczůŽ_–^XþŒ±miB[X±d 1,é”zEù»& î9gœf™9Ð'.;—™i}!ôšåîqêÛ٤ёý£½ÆA–àôe"A$˝Úsäÿ ÷Û #°xŸëí(l »ý3—¥5m! rt`†0~'j2(]S¦¦kv,ÚÇ l¦øJA£Šƒ J3E8ÙiŽ:cÉžúeZ°€¯\®kÖ(79«Ž:¯X”¾³Š&¡* ….‰Ž(ÜíŸ2¥ª‡×Hi²TF¤ò[¨íÈRëÉ䢍mgÑ.Ÿ<öäS0í„ǹÁU´f#Vß;Õ–…P@3ío<ä-±»Ž.L|kªÀê›fÂ6@»eu‚|ÓaÞÆŸ…¨ááå>åŠ?cKü6ùTÍÆ”†sĤÚ;H2RÚ†õ\Ö·Ÿn'¾ ñ#ºI¤Å´%çÁ­‚â7›‹qT3Iï¨ÖÚ5I7Ë!ÅOóŸ¶øÝñØôת¦$Tcö‘[«Ö³šÒ';Aþ ¸èíg A2Z"i¸vdÄ÷.iõ®§)¿]¤À†–‡É&ä{V¶iŽ”.Ó×Õÿ û?h¬Mt–íª[ÿ Ñÿ ÌV(í}=ibÔ¡›¥¢±b Lô¥‡piη_Z<‡z§èŒ)iÖwiÇ 2hÙ3·=’d÷8éŽ1¦¸c¤µ€7›7Ø ð\á)} ¹fËí›pAÃL%âc2 í§æQz¿;T8sæ°qø)QFMð‰XŒÂ±N¢aF¨…8¯!U  Z©RÊ ÖPVÄÀÍin™Ì-GˆªÅËŠ›•zË}º±ŽÍFò¹}Uw×#ä5B¤{î}Ð<ÙD é©¤&‡ïDbàÁôMÁ." ¤‡ú*õ'VŽ|¼´Úgllº¼klz[Æüï÷Aób‡Eÿ dÑ»Xx9ÃÜ£ÁT/`¼¸vI±Ýµ·Ë‚“G³þ*Ÿû´r|*}<¨îºœ @¦mÄ’M¹”.œ«Y–|6ÏU¤jç¥ÕÞqO ˜kDÆÁ¨5ÿ š;Њ¦¦€GÙk \ –Þ=â¼=SͧµªS°ÚÍpÜãQűÀõ¬?ÃÁ1Ñ•õZà?hóœ€ L¦l{Y*K˜Ù›zc˜–ˆâ ø+¾ ­-Ök¥%ùEÜA'}ˆ><ÊIè“bpÍ/qÞâvoX€w,\úªò6Z[XdÒæ­@Ö—€$òJí#é>'°Ú ôª˜<)4ryÙ£|óAÅn5žêŸyÒäMÝ2{"}‰–¤l÷ûWX\l¾Á¸góÉOÔ /óñB¤f¸çñ[.P˜ZsÊË*ßT܈§QN¢’¡¨§V¼(Üù*eÕ“”5T¨‹Âê¥FŒã½Dü[8'Ò¥a…Ú¶k7a *•›¼'Ò·\8¨ª\@\õ¢¦íq+DÙrmÎ…_ªæ»ŠÓœ¡¯’Ré9MÅ×D™lælffc+ŒÑ,ý™ÿ ¯þǤ=Å’Á7µ÷ÚÛ/“Ü€ñýã¼àí¾ÕÑ+ƒ,uµMâÀÄbm:ÒÎPæ{˜Gz[ƒ¯«® KHà`ßØŠéí¯P8Aq.C‰ à€kòpj´kN¶qô€…Õ,ÜNŠª-­{Zö’æû44‰sŽè‰îVíRœÕm" 6?³D9¡ÇTíÅꋇ`4«¸ÝÁô ï’ýorqКÇZ«x4Žâéþuïf¹µö[P ,Q£éaX±`PÉÍZ ¸äYúg üAx ’6Lê‚xÝÓ*äQ  Ï’¨hÍ =²,6ï#rÃ<¯–£»ƒ‹,–ê•€ aÛsñ'%Æ"®ÛüìBᝠHÚ3ß°©$“XnœÖ’î2ËTeûìxîß ¦å¿çÉ ðK§þ{‘t‚Ϋ¬jéîZ[ ”š7L¥4VÚCE×]m¤Øy”ä4-dz£œ§¸x.*ãÊÊ b÷•h:©‡¦s`BTÁRû¾g⻩‹jø sF¢àJøFl‘È•Xᓁà~*j¯ +(ÚÕ6-£¯÷GŠØy‚<Ç’.F‹Hœw(+)ÜÜâÈzÄäT§FߘãÏ;DmVœ3Àu@mÚüXÝü•3B¨òÌÁÛ<·ÃÜ z,Ì@õÅ·d2]ü8s÷IôÞ¯^Ç9¢u„~ëAŸï4«M? K]­ÅàPl@s_ p:°¬ZR”´›JC[CS.h‹ƒïËœ«Æ]–÷ó‚wR×k7X‰k›‘´ù¦=¡«‰¨¨Â')—71ó’c‡Ðúµ `é.{§p¹ój\Ž{1h{o±Ý=áUÊïGÖŒõ–-BÄm+AZX¶¡ ïHðæ¥JmÙ;…ä¡Ÿˆ¦ ° äšiÉg«$üMk5¤L“’çÊvïâï ,=f“"íἊ5ô¬x6{ɏžID0e¸vçmi'︧ºð9$ò¹÷*£’9ÿ ²TÔ…×>JV¥}Œ}$p[bÔ®*[jzS*8 ”·T›Í–ñUîƒwo$áè=LT™ç—~ô·¤ÈÚ$榍q‰„+´kFm)ž‹©i–ËqÞŠ‰à¶ü( ‚•§ •°ò·‡#5ª•µÊ﯅¡X¨šÁ*F#TXJÊ ušJVÍ&=iÄs1‚3•'fý§5Ñ<=[íÞ­ PÚ;ѱÌ_~Ä££8rÞ ²w;’hDT°>ÈG¬8Á²ÚzŽ®ò®qZcqJêäÞ-ö[ܘbň±çb“Š¶31²n×iƒðÕ;1¶þÉ ªX‰,ßqÏ$>•î íZ¥Z 1{ç൵+ƒÕµ¥°T$§K]á»Ûï*·¤tMI’ÂZbŽÕiÒ˜}bÓ0£ª5›¨ [5Ž^ÝœWøÂÝh° ¢OWun£¤5 a2Z.G2³YL]jåtì”ä ÁÓ‘%"©<ÔúÊ°sº UZvä‡ÄiÆÒM .÷V·™ø#kèýiíÌ–ª)µT[)BˆõÑ xB¾B€ÖT¨.¥~ð@VĶr#¸ü*åZNDŽH;âi ],©£öØpù(šºãö¼T.uCê•4@ÿ GÕÛ)Cx›®0ø#:ÏðFÒbR\(€€Ä®fã4Þ‰Fä¯HXƒÅ,†öEÑÔÜ]Öv²?tLÃvBY£ú6Êu5ÅAQ³1‘’¬x–HŒÐ‡ ^ ¸KwJôÖŽ5×CÚ¨vÜ«/B0$×k°=ðbÇ(Ï)w±A†Á† 11Í=èQšµ626ŒÜ/`G«µ<}—-Ö7KEHÈÉðóȤmݱû±·ø«Snmá=“ä«šmݱŸ¡¶~ó·“äUóJæúòB|E LêŽy´jDÔ$G¢þÐñ7óR8ýÒ…Ç› WVe#·Ÿ p·Fx~•ݤF÷0Èÿ K¯æS<6’¡WШ; ´ÿ ¥Êø\Òuî†åÝ–VNœkÒ7oòX¨Á­Ø÷FÎÑä±g÷ÿ M~Çî=p,X´ ÝÌÚÅ‹’ÃjÖ.ØöÏñ qïQ¤ÓZE†° =6·]܈ s¸>v•Ž^Ý\wq9r‰Î\¸¡kURÒ$­*‹Nq?Þª*!sŠÆ:TU_u±T+øX¡ ®¹¡,ÄâÃBTsÜ$Ø›4m椴zÜK]’’›Pƒ @€#â˜`é¹=I‡fiV•Ôî“nRm+µFPOhÍ0B£ €+¬5c v•:P'ÒyÎ ‰V~‚Ó†ÖuókDoh$å\*ö%Ю=£«…aȼ½÷Û.-½VŒŠ¼'lyî±1¬3ó#ÞE¿ÔS¤gV£m›=§\û"—WU¤ÚǼÿ ÂnÁGŒÃ ‚õN D³õNÚíŒÕ;HôyÄÈ©P¹Ä{:?R‘Ô¨âF÷ø£bÅó® JS|‚R÷ivýáâ€Æé¡è³´IئÑT!§˜•Øª‚¬â@q€wnïCWÄ@JU€ê¯m6]Ï:£âx'+ÒðXvÓ¦Úm=–´7œ $ì“B£~p%ÕŸUþ« N@¼üï~w˜ñø5®—'Ôe»¤5ã//€ž~‰Tþ›Å7•#¤× Íö pÄ$ùeåì*«ÓŠEØWEÈsßg ¦ûvžSsLpºÊW–âµEWöˬH; ™!CYõZ ÃÄf æ#1W. \uWâ\,\Çf j’<qTbên›Î[vxx£ë 'ö¨1›˜ÀM¼Pÿ H)ƒêêŒA7s,|F“ 꺸k³9Ìö*ç®;Ö!Ö$Eiž•¹ÒÚ†ýóéÝû¾ÕS®ó$’NÝäŸz¤5r¦ãÄÃD÷Üø!°ø‡Ô&@m™Ì^Ãä­d q5Lnÿ N;.6½·N|#ä"1Nƒx“ã<3('&ñßt  ~ªu”1Tb㫨9ê–›–bìd$ߣ=#ÕãÒmU¯eí$EFù5ýYô櫨æ왍Ǘ±ssM]·á¿0ÕåJRÓªîiƒ+O58ÖñªŠÒx" \µâá¨i’¤i —Ö ” M+M¤ë9‚‰A¦°Qõ¾ßøK~¼Ã‘g…Ö´~÷Ï[3GUœÒ½#…kàÔ®Ò”‰³·dWV‰IP‰Ú8u¹”E ÖqLj¾êÕCBš{A^Âß;–¨`¯¬ìö ˼ ×tìø.tƐm*n¨y4o&Àx¥n¦×î‡aupáÛj8¿m›è¶ã!o½;ß0y^ý×^EÑ¿ÒjzŒ­)vÚÑnÄL …^ªô× ‡—‚3k Îý­hï]içå–îÏ*÷ñþ»Ô CÒjøjÍznˆ´ ¹#b'Fô‹ ‰v¥'’à'T´ƒHýÍ%M‰ ƒ&ÆÇŒï1 ‘ –Þ ‰i¬s žR-Ÿ kŠ¬á¬7:þ 0ŒÅÒÕ/aÙ¬ÃÝ#Úøœ ©aiVc‰. ¹¦ãµ” ›Yg¦›ÆÎýº°f³7ƒhá·¸­}&D9¡ÂsÉÙÞèŠõØàC™¨ñbFC|´Ü(ŸƒÚÒ-%»'a Ì¿)ËÇn¿úÿ ÞŽX…4ÊÅH^ôΑí@ù¹Eh¶“L8Çjù ¼ÎåVªóR©Ï5uà V4lZß®=€xÖŸ–ÑÈ ÷”¨°¾__yM1tÉ?uÆþIkÄgæ@þ[¢†°XÃJ£j·:nkÅ¢u ‘}âGzö­/IµèŠ¬¼48q¦F°ŽR¼=ûì{´¯RýicS ÕÛ íNtÍÙï£,w4rêì®»~x(©Uñ§#Ñ&œÕ¤>ÎåÍÓ9’Ö{9eV­[Öjâ²ãu]˜å2›qÑšÕJç0€sÄ|Êëè0튔bÁ>“{×_F`Ø©ºê:µä,v¤ðfc1±"«ÔÍän1#=· Âøv~H½ÐßA¾¿Ü€Óš]Õ; I¾÷ç‚Qi†î¹9ywÔKG˜áñ zQY—§ÃÕZ07§X‚ Áh;ÁM)iÌCH-¯T‘ë|A0{Ò½LÚ–TâÖkÜ’dÀ“rmm»”جPF³ÖcbE§T€ÒxKºû’Ó®7±²(\4ŽÃ¸Uu@j™yĵ;³µ!Á¢b.W¤=mõ´êµK k ¸K^ÜÛ#p*Ü14qkZç5ïë †°5Ï%ÍÛ<Õ¤×Ô¥ê†C Õ´¼ú$ƒÖ“”]Ù¬qÞÚ[4©ý!ûÏ—Áb쳐XµA¬â~`›Çr¸8ìùÝ䫦<>ä÷«?xs´ÇÑ /á;¹øüÊÈÙà{"@Žïzâ¬[âß‚ U_<ÇŸ½4èN˜ú61®qŠu ¦þF£»äJ_ˆÙÎ~ ÞAã–Ý„Ï—rŠD;xTž‘ô`É«…suãO`?³à™ô Lý#Íc5öoæØ‚y´´÷«ZR§<&JÇ+éâô´€i!Àˆ0æAoàðLèÖ-2ŸõW.’t^–(KÁmHµV@xÜÇy®Ñø­â^:Ú3w· 7½¹°ñ¸â¹®:',«Mœ—n­Á+Ãbš LÈ‘ÄnRÓÅœ%¦²‰¨ùQ:¤f‚ "PÕtô¸…cæl…&˜Ú˜Ôkv‹ž+vŠ,=¢v­6—Xy*¥t£«<™:“aîϲ=¦6rO]XI¿Œ÷¤zÚ­›¶ 6÷”w\d ü~v®ˆÌk«^m<ÿ ¢‰Õ\)ùºŽ;… lîÙÅEŠ®cѾ@vnMÏ,¼“ñ•ŽBxðÃzãÇç%3ˆ"}Ù•Åî> BÉú;Ò]V+P˜F_´ßé> Øše|ï‡ÄOmFæÇ ãqÞ$/xÐx­z`ï9"œÜij‚!7.\Td…9M‡•iŽ‹¾‘50ÞŽn¥ß4ÉôO ¹*í^QêËÜÇÌ8=Ž§s‰'ÂëÙ«á%Pú[O †ÅP¯VsŽ°.‰,kc¶ ¬A9n˜XÎ-ÞšN["¹QÕ‰ƒMýÁߺXJæÍaLj¾×Ãmã¾ãÚ uñÒþåQô¦¥ /ÄUx:‚ÍÜ’ Đ©ØÝ3V¨‰ÕnÐ6ó*óúK­«…c ¯U òhsý­jóÔj#,ímŒRµ«lbïUTŒÑ8†Ä0œÏr`ð¡¬É Ї ë"À² ™ 6¥ f¶ ¢ÚoܱԷ-<Àî)†a¶ž'Ú»¨TXqØæ¶÷YÄHy˜9ÈIW­YÀuMFë ºÏ’AqÌ4·/Ú †ô'i$øä­=Ä Ý|öK×40è|È6p‘0§)o¥ctî§H+CA-“ xØ|ÐXŠç l8íºð3Ø:³¤¬KX¯UÿÙ // SPDX-License-Identifier: GPL-2.0+ // Copyright 2017 IBM Corp. #ifndef _MISC_OCXL_H_ #define _MISC_OCXL_H_ #include /* * Opencapi drivers all need some common facilities, like parsing the * device configuration space, adding a Process Element to the Shared * Process Area, etc... * * The ocxl module provides a kernel API, to allow other drivers to * reuse common code. A bit like a in-kernel library. */ #define OCXL_AFU_NAME_SZ (24+1) /* add 1 for NULL termination */ struct ocxl_afu_config { u8 idx; int dvsec_afu_control_pos; /* offset of AFU control DVSEC */ char name[OCXL_AFU_NAME_SZ]; u8 version_major; u8 version_minor; u8 afuc_type; u8 afum_type; u8 profile; u8 global_mmio_bar; /* global MMIO area */ u64 global_mmio_offset; u32 global_mmio_size; u8 pp_mmio_bar; /* per-process MMIO area */ u64 pp_mmio_offset; u32 pp_mmio_stride; u64 lpc_mem_offset; u64 lpc_mem_size; u64 special_purpose_mem_offset; u64 special_purpose_mem_size; u8 pasid_supported_log; u16 actag_supported; }; struct ocxl_fn_config { int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */ int dvsec_function_pos; /* offset of the Function DVSEC */ int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */ s8 max_pasid_log; s8 max_afu_index; }; enum ocxl_endian { OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */ OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */ OCXL_HOST_ENDIAN = 2, /**< AFU data is the same endianness as the host */ }; // These are opaque outside the ocxl driver struct ocxl_afu; struct ocxl_fn; struct ocxl_context; // Device detection & initialisation /** * Open an OpenCAPI function on an OpenCAPI device * * @dev: The PCI device that contains the function * * Returns an opaque pointer to the function, or an error pointer (check with IS_ERR) */ struct ocxl_fn *ocxl_function_open(struct pci_dev *dev); /** * Get the list of AFUs associated with a PCI function device * * Returns a list of struct ocxl_afu * * * @fn: The OpenCAPI function containing the AFUs */ struct list_head *ocxl_function_afu_list(struct ocxl_fn *fn); /** * Fetch an AFU instance from an OpenCAPI function * * @fn: The OpenCAPI function to get the AFU from * @afu_idx: The index of the AFU to get * * If successful, the AFU should be released with ocxl_afu_put() * * Returns a pointer to the AFU, or NULL on error */ struct ocxl_afu *ocxl_function_fetch_afu(struct ocxl_fn *fn, u8 afu_idx); /** * Take a reference to an AFU * * @afu: The AFU to increment the reference count on */ void ocxl_afu_get(struct ocxl_afu *afu); /** * Release a reference to an AFU * * @afu: The AFU to decrement the reference count on */ void ocxl_afu_put(struct ocxl_afu *afu); /** * Get the configuration information for an OpenCAPI function * * @fn: The OpenCAPI function to get the config for * * Returns the function config, or NULL on error */ const struct ocxl_fn_config *ocxl_function_config(struct ocxl_fn *fn); /** * Close an OpenCAPI function * * This will free any AFUs previously retrieved from the function, and * detach and associated contexts. The contexts must by freed by the caller. * * @fn: The OpenCAPI function to close * */ void ocxl_function_close(struct ocxl_fn *fn); // Context allocation /** * Allocate an OpenCAPI context * * @context: The OpenCAPI context to allocate, must be freed with ocxl_context_free * @afu: The AFU the context belongs to * @mapping: The mapping to unmap when the context is closed (may be NULL) */ int ocxl_context_alloc(struct ocxl_context **context, struct ocxl_afu *afu, struct address_space *mapping); /** * Free an OpenCAPI context * * @ctx: The OpenCAPI context to free */ void ocxl_context_free(struct ocxl_context *ctx); /** * Grant access to an MM to an OpenCAPI context * @ctx: The OpenCAPI context to attach * @amr: The value of the AMR register to restrict access * @mm: The mm to attach to the context * * Returns 0 on success, negative on failure */ int ocxl_context_attach(struct ocxl_context *ctx, u64 amr, struct mm_struct *mm); /** * Detach an MM from an OpenCAPI context * @ctx: The OpenCAPI context to attach * * Returns 0 on success, negative on failure */ int ocxl_context_detach(struct ocxl_context *ctx); // AFU IRQs /** * Allocate an IRQ associated with an AFU context * @ctx: the AFU context * @irq_id: out, the IRQ ID * * Returns 0 on success, negative on failure */ extern int ocxl_afu_irq_alloc(struct ocxl_context *ctx, int *irq_id); /** * Frees an IRQ associated with an AFU context * @ctx: the AFU context * @irq_id: the IRQ ID * * Returns 0 on success, negative on failure */ extern int ocxl_afu_irq_free(struct ocxl_context *ctx, int irq_id); /** * Gets the address of the trigger page for an IRQ * This can then be provided to an AFU which will write to that * page to trigger the IRQ. * @ctx: The AFU context that the IRQ is associated with * @irq_id: The IRQ ID * * returns the trigger page address, or 0 if the IRQ is not valid */ extern u64 ocxl_afu_irq_get_addr(struct ocxl_context *ctx, int irq_id); /** * Provide a callback to be called when an IRQ is triggered * @ctx: The AFU context that the IRQ is associated with * @irq_id: The IRQ ID * @handler: the callback to be called when the IRQ is triggered * @free_private: the callback to be called when the IRQ is freed (may be NULL) * @private: Private data to be passed to the callbacks * * Returns 0 on success, negative on failure */ int ocxl_irq_set_handler(struct ocxl_context *ctx, int irq_id, irqreturn_t (*handler)(void *private), void (*free_private)(void *private), void *private); // AFU Metadata /** * Get a pointer to the config for an AFU * * @afu: a pointer to the AFU to get the config for * * Returns a pointer to the AFU config */ struct ocxl_afu_config *ocxl_afu_config(struct ocxl_afu *afu); /** * Assign opaque hardware specific information to an OpenCAPI AFU. * * @dev: The PCI device associated with the OpenCAPI device * @private: the opaque hardware specific information to assign to the driver */ void ocxl_afu_set_private(struct ocxl_afu *afu, void *private); /** * Fetch the hardware specific information associated with an external OpenCAPI * AFU. This may be consumed by an external OpenCAPI driver. * * @afu: The AFU * * Returns the opaque pointer associated with the device, or NULL if not set */ void *ocxl_afu_get_private(struct ocxl_afu *dev); // Global MMIO /** * Read a 32 bit value from global MMIO * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @val: returns the value * * Returns 0 for success, negative on error */ int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u32 *val); /** * Read a 64 bit value from global MMIO * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @val: returns the value * * Returns 0 for success, negative on error */ int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u64 *val); /** * Write a 32 bit value to global MMIO * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @val: The value to write * * Returns 0 for success, negative on error */ int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u32 val); /** * Write a 64 bit value to global MMIO * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @val: The value to write * * Returns 0 for success, negative on error */ int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u64 val); /** * Set bits in a 32 bit global MMIO register * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @mask: a mask of the bits to set * * Returns 0 for success, negative on error */ int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u32 mask); /** * Set bits in a 64 bit global MMIO register * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @mask: a mask of the bits to set * * Returns 0 for success, negative on error */ int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u64 mask); /** * Set bits in a 32 bit global MMIO register * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @mask: a mask of the bits to set * * Returns 0 for success, negative on error */ int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u32 mask); /** * Set bits in a 64 bit global MMIO register * * @afu: The AFU * @offset: The Offset from the start of MMIO * @endian: the endianness that the MMIO data is in * @mask: a mask of the bits to set * * Returns 0 for success, negative on error */ int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset, enum ocxl_endian endian, u64 mask); // Functions left here are for compatibility with the cxlflash driver /* * Read the configuration space of a function for the AFU specified by * the index 'afu_idx'. Fills in a ocxl_afu_config structure */ int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn, struct ocxl_afu_config *afu, u8 afu_idx); /* * Tell an AFU, by writing in the configuration space, the PASIDs that * it can use. Range starts at 'pasid_base' and its size is a multiple * of 2 * * 'afu_control_offset' is the offset of the AFU control DVSEC which * can be found in the function configuration */ void ocxl_config_set_afu_pasid(struct pci_dev *dev, int afu_control_offset, int pasid_base, u32 pasid_count_log); /* * Get the actag configuration for the function: * 'base' is the first actag value that can be used. * 'enabled' it the number of actags available, starting from base. * 'supported' is the total number of actags desired by all the AFUs * of the function. */ int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported); /* * Tell a function, by writing in the configuration space, the actags * it can use. * * 'func_offset' is the offset of the Function DVSEC that can found in * the function configuration */ void ocxl_config_set_actag(struct pci_dev *dev, int func_offset, u32 actag_base, u32 actag_count); /* * Tell an AFU, by writing in the configuration space, the actags it * can use. * * 'afu_control_offset' is the offset of the AFU control DVSEC for the * desired AFU. It can be found in the AFU configuration */ void ocxl_config_set_afu_actag(struct pci_dev *dev, int afu_control_offset, int actag_base, int actag_count); /* * Enable/disable an AFU, by writing in the configuration space. * * 'afu_control_offset' is the offset of the AFU control DVSEC for the * desired AFU. It can be found in the AFU configuration */ void ocxl_config_set_afu_state(struct pci_dev *dev, int afu_control_offset, int enable); /* * Set the Transaction Layer configuration in the configuration space. * Only needed for function 0. * * It queries the host TL capabilities, find some common ground * between the host and device, and set the Transaction Layer on both * accordingly. */ int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec); /* * Request an AFU to terminate a PASID. * Will return once the AFU has acked the request, or an error in case * of timeout. * * The hardware can only terminate one PASID at a time, so caller must * guarantee some kind of serialization. * * 'afu_control_offset' is the offset of the AFU control DVSEC for the * desired AFU. It can be found in the AFU configuration */ int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control_offset, int pasid); /* * Read the configuration space of a function and fill in a * ocxl_fn_config structure with all the function details */ int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn); /* * Set up the opencapi link for the function. * * When called for the first time for a link, it sets up the Shared * Process Area for the link and the interrupt handler to process * translation faults. * * Returns a 'link handle' that should be used for further calls for * the link */ int ocxl_link_setup(struct pci_dev *dev, int PE_mask, void **link_handle); /* * Remove the association between the function and its link. */ void ocxl_link_release(struct pci_dev *dev, void *link_handle); /* * Add a Process Element to the Shared Process Area for a link. * The process is defined by its PASID, pid, tid and its mm_struct. * * 'xsl_err_cb' is an optional callback if the driver wants to be * notified when the translation fault interrupt handler detects an * address error. * 'xsl_err_data' is an argument passed to the above callback, if * defined */ int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr, u64 amr, struct mm_struct *mm, void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr), void *xsl_err_data); /* * Remove a Process Element from the Shared Process Area for a link */ int ocxl_link_remove_pe(void *link_handle, int pasid); /* * Allocate an AFU interrupt associated to the link. * * 'hw_irq' is the hardware interrupt number * 'obj_handle' is the 64-bit object handle to be passed to the AFU to * trigger the interrupt. * On P9, 'obj_handle' is an address, which, if written, triggers the * interrupt. It is an MMIO address which needs to be remapped (one * page). */ int ocxl_link_irq_alloc(void *link_handle, int *hw_irq, u64 *obj_handle); /* * Free a previously allocated AFU interrupt */ void ocxl_link_free_irq(void *link_handle, int hw_irq); #endif /* _MISC_OCXL_H_ */